Field of the Invention
The present invention relates to a method of processing a plate-shaped workpiece that includes layered bodies containing metal which are formed in superposed relation to projected dicing lines.
Description of the Related Art
Electronic equipment, typically mobile phones and personal computers, incorporates, as indispensable components, device chips that have devices such as electronic circuits, etc. thereon. A device chip is manufactured by demarcating the face side of a wafer made of a semiconductor material such as silicon or the like into a plurality of areas with a plurality of projected dicing lines also known as streets, forming devices in the respective areas, and then dividing the wafer into device chips corresponding to the devices along the projected dicing lines.
In recent years, evaluation elements referred to as TEG (Test Element Group) for evaluating electric properties of devices are often formed on projected dicing lines on wafers as described above (see, for example, Japanese Patent Laid-open No. Hei 6-349926 and Japanese Patent Laid-open No. 2005-21940). The TEG on the projected dicing lines on a wafer makes it possible to maximize the number of device chips that can be fabricated from the wafer. Once the TEG has carried out evaluations and has been made redundant, it can be removed at the same time that the wafer is severed into device chips.